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Lucien Renaud
2021-08-30 16:05:41 +02:00
commit e8877e10c7
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{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 6.0,
"width": 9.5
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.19999999999999998
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 1
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "warning",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "warning",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.09999999999999999,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.13,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": -0.0
},
"track_widths": [
0.0,
0.2
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.45,
"drill": 0.25
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
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[
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],
[
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],
[
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],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "MainBoard.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 6.0,
"clearance": 0.19,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "0.13",
"nets": [
"/PCIe_sata/AVDD0",
"/PCIe_sata/VAA1",
"/PCIe_sata/VAA2_0",
"/PCIe_sata/VAA2_1",
"/PCIe_sata/VAA2_2",
"/PCIe_sata/VAA2_3",
"/PCIe_sata/led1",
"/PCIe_sata/led2",
"/PCIe_sata/led3",
"/PCIe_sata/led4"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.13,
"via_diameter": 0.45,
"via_drill": 0.25,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "1.8",
"nets": [
"+1V8",
"VDD"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.4,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.2,
"diff_pair_gap": 0.2,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.16,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "100R",
"nets": [
"/CM4/PCIE_CLK_N",
"/CM4/PCIE_CLK_P",
"/CM4/PCIE_CLK_nREQ",
"/CM4/PCIE_RX_N",
"/CM4/PCIE_RX_P",
"/CM4/PCIE_TX_N",
"/CM4/PCIE_TX_P",
"/CM4/PCIE_nRST",
"/CM4/TRD0+",
"/CM4/TRD0-",
"/CM4/TRD1+",
"/CM4/TRD1-",
"/CM4/TRD2+",
"/CM4/TRD2-",
"/CM4/TRD3+",
"/CM4/TRD3-",
"/PCIe_sata/RX0+",
"/PCIe_sata/RX0-",
"/PCIe_sata/RX00+",
"/PCIe_sata/RX00-",
"/PCIe_sata/RX01+",
"/PCIe_sata/RX01-",
"/PCIe_sata/RX02+",
"/PCIe_sata/RX02-",
"/PCIe_sata/RX03+",
"/PCIe_sata/RX03-",
"/PCIe_sata/RX1+",
"/PCIe_sata/RX1-",
"/PCIe_sata/RX2+",
"/PCIe_sata/RX2-",
"/PCIe_sata/RX3+",
"/PCIe_sata/RX3-",
"/PCIe_sata/TX0+",
"/PCIe_sata/TX0-",
"/PCIe_sata/TX00+",
"/PCIe_sata/TX00-",
"/PCIe_sata/TX01+",
"/PCIe_sata/TX01-",
"/PCIe_sata/TX02+",
"/PCIe_sata/TX02-",
"/PCIe_sata/TX03+",
"/PCIe_sata/TX03-",
"/PCIe_sata/TX1+",
"/PCIe_sata/TX1-",
"/PCIe_sata/TX2+",
"/PCIe_sata/TX2-",
"/PCIe_sata/TX3+",
"/PCIe_sata/TX3-"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.16,
"via_diameter": 0.45,
"via_drill": 0.25,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "12V",
"nets": [
"+12V",
"+1V0"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.3,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "3.3",
"nets": [
"+3V3"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.0,
"via_diameter": 0.5,
"via_drill": 0.3,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "5V",
"nets": [
"+5V"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.5,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.13,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "90R",
"nets": [
"/CM4/OTG_ID",
"/CM4/USB+",
"/CM4/USB-",
"/PCIe_sata/SPI_CLK",
"/PCIe_sata/SPI_CS",
"/PCIe_sata/SPI_DI",
"/PCIe_sata/SPI_DO"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.147,
"via_diameter": 0.45,
"via_drill": 0.25,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "MainBoard_with_CM4.stp",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 36.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"2c979e14-b388-4161-9e61-0df9b5317aa8",
""
],
[
"2c979e14-b388-4161-9e61-0df9b5317aa8",
"PCIe_sata"
],
[
"41ea58f6-1eae-4678-a863-41eb5f7e9526",
"Etherner_USB2"
],
[
"cc4e2399-44cd-43eb-b026-ebe39d7ae688",
"Power"
],
[
"1044dfb8-d7d4-4d93-8668-ab271d88d7a4",
"CM4"
]
],
"text_variables": {}
}