2021-08-30 14:05:41 +00:00
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.09999999999999999,
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"copper_line_width": 0.19999999999999998,
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"copper_text_size_v": 1.5,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"other_line_width": 0.15,
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"other_text_thickness": 0.15,
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"pads": {
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"height": 6.0,
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"width": 9.5
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"silk_text_thickness": 0.15,
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"silk_text_upright": false,
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"zones": {
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"45_degree_only": false,
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"min_clearance": 0.19999999999999998
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}
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},
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"diff_pair_dimensions": [
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{
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"gap": 0.0,
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"width": 0.0
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}
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],
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"drc_exclusions": [],
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"meta": {
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2022-08-11 13:28:10 +00:00
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"version": 2
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2021-08-30 14:05:41 +00:00
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "warning",
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"diff_pair_gap_out_of_range": "warning",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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2022-08-11 13:28:10 +00:00
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"footprint_type_mismatch": "error",
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2021-08-30 14:05:41 +00:00
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "ignore",
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"silk_overlap": "ignore",
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"skew_out_of_range": "error",
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2022-08-11 13:28:10 +00:00
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"through_hole_pad_without_hole": "error",
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2021-08-30 14:05:41 +00:00
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "warning",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rules": {
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"allow_blind_buried_vias": false,
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"max_error": 0.005,
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"min_clearance": 0.09999999999999999,
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"min_copper_edge_clearance": 0.0,
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"min_hole_clearance": 0.0,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.19999999999999998,
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"min_track_width": 0.13,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.39999999999999997,
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2022-08-11 13:28:10 +00:00
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"use_height_for_length_calcs": true
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2021-08-30 14:05:41 +00:00
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},
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"track_widths": [
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0.0,
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2022-08-11 13:28:10 +00:00
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0.15,
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2021-08-30 14:05:41 +00:00
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0.2
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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},
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{
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"diameter": 0.45,
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"drill": 0.25
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}
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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"layer_presets": []
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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"erc": {
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"meta": {
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"version": 0
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"rule_severities": {
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"bus_definition_conflict": "error",
|
2022-05-25 18:13:38 +00:00
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"bus_entry_needed": "error",
|
2021-08-30 14:05:41 +00:00
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"wire_dangling": "error"
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}
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "MainBoard.kicad_pro",
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"version": 1
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"net_settings": {
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"classes": [
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{
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"wire_width": 6.0
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},
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{
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"bus_width": 6.0,
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"clearance": 0.15,
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"diff_pair_gap": 0.25,
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"name": "0.13",
|
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|
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"nets": [
|
|
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|
|
"/PCIe_sata/AVDD0",
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"/PCIe_sata/VAA1",
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"/PCIe_sata/VAA2_0",
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"/PCIe_sata/VAA2_1",
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"/PCIe_sata/VAA2_2",
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"/PCIe_sata/VAA2_3",
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"/PCIe_sata/led1",
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"/PCIe_sata/led2",
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"/PCIe_sata/led3",
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"/PCIe_sata/led4"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"wire_width": 6.0
|
|
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},
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{
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"bus_width": 6.0,
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"clearance": 0.2,
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"microvia_drill": 0.1,
|
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|
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"name": "1.8",
|
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|
|
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"nets": [
|
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|
|
|
"+1V8",
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|
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"VDD"
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|
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.4,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
|
|
|
|
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},
|
|
|
|
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{
|
|
|
|
|
"bus_width": 6.0,
|
|
|
|
|
"clearance": 0.2,
|
|
|
|
|
"diff_pair_gap": 0.2,
|
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|
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"diff_pair_via_gap": 0.25,
|
|
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|
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"diff_pair_width": 0.16,
|
|
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|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "100R",
|
|
|
|
|
"nets": [
|
|
|
|
|
"/CM4/PCIE_CLK_N",
|
|
|
|
|
"/CM4/PCIE_CLK_P",
|
|
|
|
|
"/CM4/PCIE_CLK_nREQ",
|
|
|
|
|
"/CM4/PCIE_RX_N",
|
|
|
|
|
"/CM4/PCIE_RX_P",
|
|
|
|
|
"/CM4/PCIE_TX_N",
|
|
|
|
|
"/CM4/PCIE_TX_P",
|
|
|
|
|
"/CM4/PCIE_nRST",
|
|
|
|
|
"/CM4/TRD0+",
|
|
|
|
|
"/CM4/TRD0-",
|
|
|
|
|
"/CM4/TRD1+",
|
|
|
|
|
"/CM4/TRD1-",
|
|
|
|
|
"/CM4/TRD2+",
|
|
|
|
|
"/CM4/TRD2-",
|
|
|
|
|
"/CM4/TRD3+",
|
|
|
|
|
"/CM4/TRD3-",
|
|
|
|
|
"/PCIe_sata/RX0+",
|
|
|
|
|
"/PCIe_sata/RX0-",
|
|
|
|
|
"/PCIe_sata/RX00+",
|
|
|
|
|
"/PCIe_sata/RX00-",
|
|
|
|
|
"/PCIe_sata/RX01+",
|
|
|
|
|
"/PCIe_sata/RX01-",
|
|
|
|
|
"/PCIe_sata/RX02+",
|
|
|
|
|
"/PCIe_sata/RX02-",
|
|
|
|
|
"/PCIe_sata/RX03+",
|
|
|
|
|
"/PCIe_sata/RX03-",
|
|
|
|
|
"/PCIe_sata/RX1+",
|
|
|
|
|
"/PCIe_sata/RX1-",
|
|
|
|
|
"/PCIe_sata/RX2+",
|
|
|
|
|
"/PCIe_sata/RX2-",
|
|
|
|
|
"/PCIe_sata/RX3+",
|
|
|
|
|
"/PCIe_sata/RX3-",
|
|
|
|
|
"/PCIe_sata/TX0+",
|
|
|
|
|
"/PCIe_sata/TX0-",
|
|
|
|
|
"/PCIe_sata/TX00+",
|
|
|
|
|
"/PCIe_sata/TX00-",
|
|
|
|
|
"/PCIe_sata/TX01+",
|
|
|
|
|
"/PCIe_sata/TX01-",
|
|
|
|
|
"/PCIe_sata/TX02+",
|
|
|
|
|
"/PCIe_sata/TX02-",
|
|
|
|
|
"/PCIe_sata/TX03+",
|
|
|
|
|
"/PCIe_sata/TX03-",
|
|
|
|
|
"/PCIe_sata/TX1+",
|
|
|
|
|
"/PCIe_sata/TX1-",
|
|
|
|
|
"/PCIe_sata/TX2+",
|
|
|
|
|
"/PCIe_sata/TX2-",
|
|
|
|
|
"/PCIe_sata/TX3+",
|
|
|
|
|
"/PCIe_sata/TX3-"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.16,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.25,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 6.0,
|
|
|
|
|
"clearance": 0.2,
|
|
|
|
|
"diff_pair_gap": 0.25,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.2,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "12V",
|
|
|
|
|
"nets": [
|
|
|
|
|
"+12V",
|
|
|
|
|
"+1V0"
|
|
|
|
|
],
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|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 1.3,
|
|
|
|
|
"via_diameter": 0.8,
|
|
|
|
|
"via_drill": 0.4,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 6.0,
|
|
|
|
|
"clearance": 0.2,
|
|
|
|
|
"diff_pair_gap": 0.25,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.2,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "3.3",
|
|
|
|
|
"nets": [
|
|
|
|
|
"+3V3"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 1.0,
|
|
|
|
|
"via_diameter": 0.5,
|
|
|
|
|
"via_drill": 0.3,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 6.0,
|
|
|
|
|
"clearance": 0.2,
|
|
|
|
|
"diff_pair_gap": 0.25,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.2,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "5V",
|
|
|
|
|
"nets": [
|
|
|
|
|
"+5V"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 1.5,
|
|
|
|
|
"via_diameter": 0.8,
|
|
|
|
|
"via_drill": 0.4,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"bus_width": 6.0,
|
|
|
|
|
"clearance": 0.13,
|
|
|
|
|
"diff_pair_gap": 0.25,
|
|
|
|
|
"diff_pair_via_gap": 0.25,
|
|
|
|
|
"diff_pair_width": 0.15,
|
|
|
|
|
"line_style": 0,
|
|
|
|
|
"microvia_diameter": 0.3,
|
|
|
|
|
"microvia_drill": 0.1,
|
|
|
|
|
"name": "90R",
|
|
|
|
|
"nets": [
|
|
|
|
|
"/CM4/OTG_ID",
|
|
|
|
|
"/CM4/USB+",
|
|
|
|
|
"/CM4/USB-",
|
|
|
|
|
"/PCIe_sata/SPI_CLK",
|
|
|
|
|
"/PCIe_sata/SPI_CS",
|
|
|
|
|
"/PCIe_sata/SPI_DI",
|
|
|
|
|
"/PCIe_sata/SPI_DO"
|
|
|
|
|
],
|
|
|
|
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
|
|
|
|
"track_width": 0.147,
|
|
|
|
|
"via_diameter": 0.45,
|
|
|
|
|
"via_drill": 0.25,
|
|
|
|
|
"wire_width": 6.0
|
|
|
|
|
}
|
|
|
|
|
],
|
|
|
|
|
"meta": {
|
2022-05-25 18:13:38 +00:00
|
|
|
"version": 2
|
2021-08-30 14:05:41 +00:00
|
|
|
},
|
|
|
|
|
"net_colors": null
|
|
|
|
|
},
|
|
|
|
|
"pcbnew": {
|
|
|
|
|
"last_paths": {
|
|
|
|
|
"gencad": "",
|
|
|
|
|
"idf": "",
|
|
|
|
|
"netlist": "",
|
|
|
|
|
"specctra_dsn": "",
|
|
|
|
|
"step": "MainBoard_with_CM4.stp",
|
|
|
|
|
"vrml": ""
|
|
|
|
|
},
|
|
|
|
|
"page_layout_descr_file": ""
|
|
|
|
|
},
|
|
|
|
|
"schematic": {
|
2022-05-25 18:13:38 +00:00
|
|
|
"annotate_start_num": 0,
|
2021-08-30 14:05:41 +00:00
|
|
|
"drawing": {
|
|
|
|
|
"default_bus_thickness": 12.0,
|
|
|
|
|
"default_junction_size": 36.0,
|
|
|
|
|
"default_line_thickness": 6.0,
|
|
|
|
|
"default_text_size": 50.0,
|
|
|
|
|
"default_wire_thickness": 6.0,
|
|
|
|
|
"field_names": [],
|
2021-08-30 21:20:42 +00:00
|
|
|
"intersheets_ref_own_page": false,
|
2021-08-30 14:05:41 +00:00
|
|
|
"intersheets_ref_prefix": "",
|
|
|
|
|
"intersheets_ref_short": false,
|
|
|
|
|
"intersheets_ref_show": false,
|
|
|
|
|
"intersheets_ref_suffix": "",
|
|
|
|
|
"junction_size_choice": 3,
|
2022-05-25 18:13:38 +00:00
|
|
|
"label_size_ratio": 0.3,
|
2021-08-30 14:05:41 +00:00
|
|
|
"pin_symbol_size": 25.0,
|
|
|
|
|
"text_offset_ratio": 0.3
|
|
|
|
|
},
|
|
|
|
|
"legacy_lib_dir": "",
|
|
|
|
|
"legacy_lib_list": [],
|
|
|
|
|
"meta": {
|
2022-05-25 18:13:38 +00:00
|
|
|
"version": 1
|
2021-08-30 14:05:41 +00:00
|
|
|
},
|
|
|
|
|
"net_format_name": "",
|
2022-05-25 18:13:38 +00:00
|
|
|
"ngspice": {
|
|
|
|
|
"fix_include_paths": true,
|
|
|
|
|
"fix_passive_vals": false,
|
|
|
|
|
"meta": {
|
|
|
|
|
"version": 0
|
|
|
|
|
},
|
|
|
|
|
"model_mode": 0,
|
|
|
|
|
"workbook_filename": ""
|
|
|
|
|
},
|
2021-08-30 14:05:41 +00:00
|
|
|
"page_layout_descr_file": "",
|
|
|
|
|
"plot_directory": "",
|
|
|
|
|
"spice_adjust_passive_values": false,
|
|
|
|
|
"spice_external_command": "spice \"%I\"",
|
|
|
|
|
"subpart_first_id": 65,
|
|
|
|
|
"subpart_id_separator": 0
|
|
|
|
|
},
|
|
|
|
|
"sheets": [
|
|
|
|
|
[
|
2021-08-30 21:20:42 +00:00
|
|
|
"63d118ed-597f-4486-8d92-30ed5c54c668",
|
2021-08-30 14:05:41 +00:00
|
|
|
""
|
|
|
|
|
],
|
|
|
|
|
[
|
|
|
|
|
"2c979e14-b388-4161-9e61-0df9b5317aa8",
|
|
|
|
|
"PCIe_sata"
|
|
|
|
|
],
|
|
|
|
|
[
|
|
|
|
|
"41ea58f6-1eae-4678-a863-41eb5f7e9526",
|
|
|
|
|
"Etherner_USB2"
|
|
|
|
|
],
|
|
|
|
|
[
|
|
|
|
|
"cc4e2399-44cd-43eb-b026-ebe39d7ae688",
|
|
|
|
|
"Power"
|
|
|
|
|
],
|
|
|
|
|
[
|
|
|
|
|
"1044dfb8-d7d4-4d93-8668-ab271d88d7a4",
|
|
|
|
|
"CM4"
|
|
|
|
|
]
|
|
|
|
|
],
|
|
|
|
|
"text_variables": {}
|
|
|
|
|
}
|
